Design Verification Engineer
This vacancy is published by an accredited employer with authorized corporate payroll and standard compliance adherence.
Transatlantic Cost of Living & Purchasing Power Benchmark
Position Overview & Specifications
Summary
Key Qualifications
- Expertise with verification languages such as SystemVerilog, Specman or Vera and verification methodologies such as UVM/OVM is a plus.
- Experience of working in complex ASIC or SoC designs
- Expertise with HDL simulators & waveform viewers
- Experience defining coverage space, writing coverage model, analyzing results
- Experience working under strict schedule deadlines with the ability to handle multiple priorities
- Graphics architecture and programming (OpenGL/OpenCL) highly desired. Strong knowledge of computer architecture, general purpose microprocessor and memory sub-system micro-architecture in lieu of graphics experience.
- Experience with scripting languages like Python, Go, Perl or Ruby is a plus
- Excellent communication skills and ability to collaborate
Description
Education & Experience
Additional Requirements
- Successful candidates based in Cambridge will be working as part of a wider Cambridge / St Albans team. Travel to St Albans will be required from time to time .
Candidate Selection & Onboarding Process
Application & Resume Screening
Submit your tailored CV/Resume directly to the talent acquisition portal.
Technical & Competency Interviews
Virtual interviews with the hiring manager and multidisciplinary team.
Formal Offer & Benefits Negotiation
Written agreement outlining compensation, equity, retirement vesting, and relocation allowances.
Onboarding & Corporate Integration
Equipment provisioning, team orientation, and commencement of duties.
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Design Verification Engineer • Apple
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